Recently, packages of components such as semiconductor integrated circuits, transistors, diodes and the like are downsized and made thin. In such components, existence of connecting leads gives large influence on the package size. Therefore, there is proposed a surface mount type semiconductor device having a lead-less structure in which connecting leads are not used. Especially, in a semiconductor integrated circuit device, it is required that a disposition pitch of connecting leads of a lead frame is minute, in order to realize a device having many lead pins. Also, width or thickness of each lead must be reduced and there is a possibility that the leads bend easily, causing short circuit between the leads. Alternatively, it is required that the package size is enlarged to realize a large disposition pitch of the leads.
Japanese patent laid-open publication No. 9-162348 discloses a semiconductor device having such lead-less structure. FIG. 40 is a cross sectional view of the semiconductor device disclosed in Japanese patent laid-open publication No. 9-162348. As shown in FIG. 40, a semiconductor element (element chip) 303 is fixed onto an element fixing resin board 301, and the upper side and peripheral area of the semiconductor element 303 are molded by package resin 305. Also, there are provided a plurality of projected portions 307 on the bottom surface of the package resin 305. The surface of each of the projected portions 307 is coated by a metal film 309. The metal films 309 are electrically coupled with the semiconductor element 303 via bonding wires 311, within the package resin 305. Thereby, the metal films 309 function as mounting electrodes for mounting the semiconductor device onto a printed circuit board and the like. Thus, in the semiconductor device shown in FIG. 40, mounting electrodes are formed directly on the bottom surface of the package, and it is not necessary to use a lead-frame. Therefore, it is possible to avoid the above-mentioned disadvantages caused by the lead-frame. Also, the package is effectively downsized and made thin.
Japanese patent laid-open publication No. 9-252014 discloses another semiconductor device of this type. FIG. 41 is a cross sectional view of a semiconductor device disclosed in Japanese patent laid-open publication No. 9-252014. The semiconductor device of FIG. 41 is fabricated as follows. First, a metal foil is shaped into predetermined patterns to form a die pad portion 401 and a plurality of electrode portions 403. On the die pad portion 401, a semiconductor element 405 is mounted by using mounting material 407. The electrode portions 403 are then electrically coupled with the semiconductor element 405 by using bonding wires 409. Thereafter, the semiconductor element 405 and the bonding wires 409 are molded by package resin 411. In the semiconductor device shown in FIG. 41, the electrode portions 403 are exposed at the bottom surface of the package resin 411. Thereby, it is possible to realize a surface mount type semiconductor device having a lead-less structure. Thus, it is possible to downsize and thin down the package. In Japanese patent laid-open publication No. 9-252014, a method is also disclosed in which, before patterning a metal foil, a semiconductor element is mounted on the metal foil and wire bonding is performed, and thereafter the metal foil is patterned into desired patterns. Also, Japanese patent laid-open publication No. 10-22440 discloses a technology similar to that described above.
Further, there is known a technology disclosed in Japanese patent laid-open publication No. 8-115989 and Japanese patent laid-open publication No. 8-115991. FIG. 42 is a cross sectional view of a semiconductor device disclosed in Japanese patent laid-open publication No. 8-115989 and Japanese patent laid-open publication No. 8-115991. The semiconductor device shown in FIG. 42 has a frame-like terminal portion 501, and a plurality of column-like terminal portions 503 which are disposed within the frame-like terminal portion 501 and which are insulated from each other and from the frame-like terminal portion 501 via resin portion 505. A semiconductor element 509 is disposed on a patterned layer 507 formed on the frame-like terminal portion 501 and the column-like terminal portions 503. The semiconductor element 509 is electrically coupled with the patterned layer 507 via bonding wires 511. Thereby, the semiconductor element 509 is electrically coupled with the column-like terminal portions 503 via conducting pattern portions of the patterned layer 507. Further, the semiconductor element 509, the bonding wires 511 and the like are molded by resin 513. In this semiconductor device, the column-like terminal portions 503 are disposed in an area just under the semiconductor element 509 as electrodes for mounting. Therefore, it is possible to realize a semiconductor device having a grid array structure.
In each of the conventional semiconductor devices mentioned above, a relatively large number of fabrication steps are required and fabrication process becomes complicated, thereby manufacturing costs are increased. That is, in the semiconductor device shown in FIG. 40, it is necessary to provide the projected portions 307 at the bottom surface of the package resin 305, and to form the metal film 309 on the surface of the projected portions 307. The method of manufacturing such semiconductor device disclosed in Japanese patent laid-open publication No. 9-162348 is as follows. First, a metal base member is formed in which recessed portions are provided at portions corresponding to the projected portions 307. The metal film 309 is then selectively formed in each of the recessed portions. Then, mounting of the semiconductor element 303 and electrical connection between the semiconductor element 303 and the metal film 309 via bonding wires 311 are performed. Thereafter, molding by the package resin 305 is performed. The metal base member is finally removed to fabricate the semiconductor device. In this method, number of processes for selectively forming the metal film 309 is relatively large, and it is necessary to use the metal base member which becomes unnecessary after the completion of manufacturing. Therefore, manufacturing cost of the semiconductor device becomes large.
In the semiconductor device shown in FIG. 41, an etching process is required to pattern a metal foil into desired patterns when the die pad portions 401 and the electrode portions 403 are formed. Therefore, manufacturing process becomes complicated. Also, it is necessary to use a base member for supporting the metal foil when the metal foil is patterned. Since this base member becomes unnecessary after manufacturing the semiconductor device, it causes an increase in the manufacturing cost of the semiconductor device, as in the semiconductor device shown in FIG. 40. When the metal foil is patterned after packaging the semiconductor element, the base member becomes unnecessary. However, since the etching process is performed by wet etching, it is necessary to perform water-resistant protection of the package when the etching is performed. Therefore, manufacturing process becomes complicated and, in this respect, manufacturing costs of the semiconductor device become large.
Further, in the semiconductor device shown in FIG. 42, the pattern layer 507 is required between the frame-like terminal portion and the column-like terminal portions 501 and 503 and the semiconductor element 509 mounted thereon for selectively and electrically coupling the bonding wires 511 with the column-like terminal portions 503. Therefore, a large number of components are required and manufacturing costs of the semiconductor device become large. Also, number of manufacturing processes increases and manufacturing process becomes complicated.
Also, the above-mentioned conventional semiconductor devices have common problems as follows. In order to fabricate the above-mentioned semiconductor devices, components such as the metal film portions 309, the electrode portions 403 each made of a metal foil, the column-like terminal portions 503, the pattern layer 507 and the like are required as mounting terminals. It is necessary that these components are previously designed and manufactured into predetermined electrode arrangement patterns and sizes in compliance with kinds and sizes of the semiconductor elements 303, 405 and 509. Therefore, when a semiconductor element having different kind or size is to be mounted, it is necessary to again design and fabricate the above-mentioned components having different patterns and sizes. Also, when the components are to be previously fabricated and prepared, it is necessary to prepare a plurality kinds of components applicable to a plurality kinds or sizes of semiconductor elements. Therefore, manufacturing and management of the components used for fabricating the semiconductor devices become complicated.